1. Field of the Invention
The present invention relates to a method for fabricating a metal oxide semiconductor field effect transistor (MOSFET) In particular, the invention relates to a method for fabricating a MOSFET, using a damascene process, with the aim of suppressing leakage current and enhancing a sub-threshold characteristic of the MOSFET.
2. Description of the Prior Art
A MOSFET fabricating technique using the damascene process to form a gate electrode has heretofore been known. This technique is disclosed in, for example, Kokai (Japanese Unexamined Patent Publication) No. Hei 8-37296 (No. 37296 of 1996). FIGS. 10A through 10C, 11A through 11C, and 12A through 12C are schematic cross-sectional diagrams illustrating sequential steps of fabricating a MOSFET by the above prior art.
As is shown in FIG. 10A, field oxide layers 102 for device isolation are first formed on a p-type silicon substrate 101. On the p-type silicon substrate 101, then, an insulation layer 103 into which n-type impurities are incorporated is formed. For the insulation layer 103, for example, a phosphor-silicate glass (PSG) film deposited up to a thickness of about 400 nm by low pressure-chemical vapor deposition (LP-CVD) is used.
Next, as is shown in FIG. 10B, a resist pattern 104 for forming a gate electrode on the insulation layer 103 is formed. This resist pattern 104 has an opening 104a that is formed in a part of a region above the region where the field oxide layers 102 are not present.
Then, as is shown in FIG. 10C, using the resist pattern 104 as a mask, the insulation layer 103 existing beneath the opening 104a is anisotropically etched and removed by a reactivity ion etching (RIE) process, so that the p-type silicon substrate 101 is exposed at the bottom of the opening 104a. Inconsequence, a trench 105 is formed in which a gate electrode will be embedded.
Next, as is shown in FIG. 11A, PSG is deposited over the entire surface of the silicon substrate 101 by the LP-CVD to form a PSG layer 106 with a thickness of about 100 nm. At this time, the phosphor (P) concentration in the PSG layer 106 is made lower than that in the insulation layer 103. Then, as is shown in FIG. 11B, by etching back the PSG layer 106, the PSG layer 106 portions at the bottom of the trench 105 and covering the insulation layer 103 are removed. In consequence, PSG layers for spacers 106a are formed on the side walls of the trench 105. Then, as is shown in FIG. 11C, a gate insulation layer 107 is formed on the surface of the p-type silicon substrate 101 in the bottom of the trench 105 by a thermal oxidation process.
Next, as is shown in FIG. 12A, by a thermomigration process, P is diffused from the insulation layer 103 and the PSG layers for spacers 106a, so that source/drain regions 108 are formed. The source/drain regions 108 each consist of an n+ layer 108a and an nxe2x88x92 layer 108b. The n+ layer 108a is formed by the P diffusion from the insulation layer 103. The nxe2x88x92 layer 108b is formed by the P diffusion from either PSG layer 106 for spacer.
Next, as in shown in FIG. 12B, material of low resistance such as tungsten (wolfram) (W) is deposited over the entire surface of the silicon substrate 101 to form a conductive layer 109 with a thickness of about 600 nm. Then, as is shown in FIG. 12C, by chemical mechanical polishing (CMP), the conductive layer 109, insulation layer 103, PSG layers 106a for spacers are polished so that they are partially removed and a planar top surface is created. In consequence, a damascene gate electrode 109 a made of W is formed. In the manner described above, a MOSFET is fabricated.
With this technique disclosed in the above-mentioned Kokai No. Hei 8-37296, however, there are the following two problems. A first problem is that leakage current called a gate induced drain leakage (GIDL) current occurs in the end of the drain region. This occurs due to a strong electric field generated between the gate electrode and the end of the drain region; in other words, a tunneling phenomenon gives rise to the leakage current. In up-to-date MOSFETs, the gate insulation layer becomes thinner as smaller devices are required. This results in generating a strong electric field between the gate electrode and the end of the drain region and the GIDL occurrence becomes more significant.
A second problem is that the thickness of the gate insulation layer near a field oxide layer is made thinner and this causes a hump in a sub-threshold characteristic of the device. FIG. 13 is a cross-sectional view of a MOSFET fabricated by the prior art method in which a gate electrode is located to partially contact with a field oxide layer. FIG. 14 is a graph representing a sub-threshold characteristic of the MOSFET shown in FIG. 13 with gate voltages plotted on the abscissa and drain currents on the ordinate. The reason why a hump occurs in the sub-threshold characteristic of the device will be explained below, using FIGS. 13 and 14. In FIG. 13, components corresponding to those shown in FIGS. 10 through 12 are assigned the same reference numbers and their detailed explanation is not repeated.
As is shown in FIG. 13, in the MOSFET having a field oxide layer 102 formed, using shallow trench isolation (STI), a dent 111 called a divot is sometimes made at the end of the STI layer 110. This is due to that the STI layer is etched during a resist stripping process or the like. The corner of the silicon substrate 101 adjacent to the field oxide layer 102 is rounded and the gate insulation layer 107 formed by thermal oxidation becomes thinner at this corner.
For the MOSFET having the gate insulation layer 107 that is partially thinner, a hump occurs in its sub-threshold characteristic. That is, a very small current tends to flow through it even if the gate voltage is lower than its threshold voltage. In the graph of FIG. 14, a solid line 112 represents the sub-threshold characteristic of the MOSFET without a hump occurring and a dotted line 113 represents the sub-threshold characteristic of the MOSFET with a hump occurring. As is apparent in FIG. 14, the sub-threshold characteristic with a hump is inferior to that without a hump and lowers the turn-on performance of the MOSFET. This phenomenon appears significantly for a static random access memory (SRAM) or the like using relatively short transistors.
Meanwhile, Kokai (Japanese Unexamined Patent Publication) No. Hei 10-64898 (No. 64898 of 1998) discloses a technique in which halogen ions are implanted in the surface layer or silicon layer of a silicon substrate and then a gate oxide layer is formed by performing a heating process. According to this disclosure, the implanted halogen accelerates silicon oxidation so that a thicker and uniform oxide layer can be formed. Also, Kokai (Japanese Unexamined Patent Publication) No. Hei 11-354648 (No. 354648 of 1999) and Kokai (Japanese Unexamined Patent Publication) No. 2001-237324 disclose a technique in which halogen or inert gas ions are implanted in the surface layer of a silicon substrate and then a gate oxide layer is formed by a heating process. According to this disclosure, because the implanted ions can accelerate oxidation reaction, the thickness of the gate oxide layer can be controlled by adjusting the quantity of the ions to be implanted. To solve the above-noted problems, therefore, it is conceivable to form a thicker gate oxide layer, using these techniques.
However, a problem associated with the above-mentioned prior art techniques is as follows: making the gate insulation layer thicker causes a decrease in the MOSFET operation speed and an increase in its power consumption and makes it difficult to develop a smaller MOSFET.
The present invention provides a method for fabricating a MOSFET comprising the steps of forming a first insulation layer over a semiconductor substrate; forming a trench which bottoms on the semiconductor substrate in the first insulation layer so that the semiconductor substrate is exposed at the bottom of the trench; injecting impurities selectively under at least one end of the exposed surface of the semiconductor substrate; forming a second insulation layer to cover the bottom surface of the trench by oxidizing the exposed surface of the semiconductor substrate; forming a gate electrode over the second insulation layer inside the trench; removing the first insulation layer; forming a drain region under the surface of the semiconductor substrate so that the drain region contacts with one end of the second insulation layer, the end under which the impurities were injected; and forming a source region under the surface of the semiconductor substrate so that the source region contacts with the other end of the second insulation layer, the end opposite to the end under which the impurities were injected.